AMD K10 secrets revealed

A.Rafay

Seasoned
Jan 24, 2007
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Karachi
1. First of all, the K10 has an integrated DDR2 memory controller with memory prefetcher

2. K10 core has 64kb of L1 instruction cache + 64 KB data cache.

3. It also has on chip L2 and L3 cache and this varies depending on the core.

4. The Barcelona / Agena quad core K10 for example has 4x512 KB L2 and 2 MB of L3 cache.

5. K10 supports 32 Byte instruction fetch, instruction precode and branch prediction during cache line files, decoupled decode / execution code, 3-way AMD64 instruction decoding, sideband stack optimizer, dynamic scheduling and speculative execution.

6. The new core also features 3-way integer execution and address generation, 3-way 128 bit wide floating point executions, Enhanced 3Dnow! Micro architecture, MMX, SSE, SSE2, SSE3 & SSE4A Single instruction multiple data (SIMD) instruction extensions.

7. Further the CPU can cope with advanced bit manipulation instructions, super forwarding, prefetch into L1 data cache, deep out of order integer & floating point execution, 8 additional XMM registers (SSE, SSE2, SSE3 and SSE4A) & 8 additional GPRs in 64 Bit mode.

8. Last but not the least is Enhanced HyperTransport micro architecture. If this is too much for you don’t worry, it is too much for most of us, but we like that the K10 supports SSE4A so it might have a fighting chance in encoding.


i'll post some more details and terminologies later........
 
Last edited:

Atif

Ancient Philosopher
Jan 18, 2007
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From Mars
What does mean by this "the K10 has an integrated DDR2 memory controller with memory prefetcher"?
 

A.Rafay

Seasoned
Jan 24, 2007
4,392
6
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Karachi
as u know AMD's processors have integrated memory controllers... this means no going towards bridge when accessing RAM..... it decreases time substantially.... AMD came up with this neat trick when athlon was launched..... K10s have DDR2-1066 controllers builtin....

previously some K8 had problems acessing DDR2-800 e.g. 5000+X2 recognized DDR-2 800 as DDR2-742 this caused system to slow down.... solution was to overclock.... but now scence has changed... support is added for upto 1066 Mhz


memory prefetching has 3 steps

First, is it important to check the caches while searching for the prefetched data, or can one skip the caches and go straight to main memory? Second, should prefetched data be placed directly into the primary data cache, or somewhere further down in the cache hierarchy? Finally, decide whether place prefetched data in a separate target buffer or in normal cache hierarchy


these 2 things are builtin so expect something but not a miracle
 
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